1. The Field of the Invention
The present invention relates to methods for forming patterned dielectric regions on semiconductor wafers. More particularly, the present invention relates to methods of locally oxidizing silicon substrates of semiconductor wafers to grow patterned regions of oxide without the formation of bird's beak structures and without the need for reflowing the oxide. The method of the present invention is particularly useful in forming thin, submicron-sized, patterned oxide regions for use as spacers and gate oxides of MOS integrated circuits.
2. The Relevant Technology
Integrated circuits are currently manufactured by an elaborate process in which scores of electronic devices are integrally formed on semiconductor wafers. The conventional electronic devices formed on a semiconductor wafer in the process of fabricating integrated circuits include capacitors, resistors, transistors, diodes, and the like. In advanced integrated circuit manufacturing processes, hundreds of thousands of these electronic devices are formed on a single semiconductor wafer.
One frequently conducted portion of the process of manufacturing an integrated circuit is the formation of an insulating layer on a silicon substrate of a semiconductor wafer from which the integrated circuit is formed. Insulating layers are frequently formed from oxides of silicon, typically silicon dioxide (SiO.sub.2). Silicon dioxide and related oxides of silicon such as borophosphosilicate glass (BPSG) are considered advantageous for forming insulating layer, due to the simplicity of the processes by which they are grown. For example, when forming a blanket oxide layer, or "field oxide," a silicon substrate is simply exposed to oxygen or oxygen containing gases or liquids, usually at an elevated temperature, and the oxide grows from the resulting reaction. This simple process is greatly complicated, however, when patterned or "local" oxide regions are to be formed on the semiconductor wafer.
Applications where patterned oxide regions are used in the integrated circuit manufacturing process include the formation of passivation layers between devices located on different levels of the semiconductor wafer, the formation of spacers between electronic devices located on the same level of the semiconductor wafer, and the formation of thin gate oxides for use in MOS transistors. In forming such layers, one of two basic processes is conventionally used, namely chemical vapor deposition and thermal oxidation.
Chemical vapor deposition typically involves the pyrolytic decomposition of a silicon-containing precursor material in a chemical vapor deposition chamber. One frequently used precursor material from which the silicon oxide is decomposed comprises tetraethylorthosilicate (Si(C.sub.2 H.sub.5).sub.4), also known as TEOS. In the decomposition process, the precursor material is reacted under high temperature with oxygen to result in the growth of a layer of silicon dioxide together with easily removed byproducts.
In order to form patterned silicon dioxide regions with chemical vapor deposition, an underlying silicon substrate is first patterned so as to form recesses in the topography thereof, such as trenches and holes. The precursor layer is then grown as a blanket oxide layer. Dopants are normally added to form a layer of BPSG, which reflows at lower temperatures than undoped silicon dioxide over the patterned silicon layer. The BPSG is later reflowed to completely fill the recesses in the topography of the silicon substrate and leave a planar surface. The portion of the silicon oxide above the recesses is then removed with an etch-back process or by chemical mechanical polishing.
One problem with the conventional chemical vapor deposition process for forming patterned oxide regions is that numerous steps are required to pattern the insulating regions. The numerous steps add significantly to the complexity and expense of the integrated circuit manufacturing process.
The conventional method of forming patterned insulating regions with thermal oxidation is referred to as the Local Oxidation of Silicon (LOCOS) and involves masking a silicon substrate and exposing the unmasked portions of the silicon substrate to air or water vapor at temperatures of about 900.degree. C. to 1200.degree. C. As continued exposure to heat damages crystalline structures within the integrated circuit wafer or the devices located thereon, a process of rapid thermal processing (RTP) is used to ramp the temperature of the wafer up and down quickly. Rapid thermal processing has the drawback of reduced throughput, as the wafers must be processed one at a time.
Another drawback to the LOCOS process is illustrated in FIG. 1. Under the LOCOS process, the silicon substrate is patterned using nitride spacers. The patterning arrangement is shown in FIG. 1, where a silicon substrate 12 is situated on a semiconductor wafer 10. Formed on silicon substrate 12 is a patterned silicon nitride mask layer 14. Subsequent exposure of semiconductor wafer 10 to oxygen through silicon nitride mask layer 14 at an elevated temperature results in the growth of silicon dioxide spacers 16 in the areas of silicon substrate 12 that are not covered by silicon nitride mask layer 14.
Silicon dioxide spacers 16 are typically thicker at the center and taper toward the edges, forming what are known as "bird's beak" structures 18 at the far edges. Bird's beak structures 18 tend to undercut silicon nitride mask 14, causing a deviation in the critical dimensions to be maintained during subsequent etch steps. The nonuniform shape of silicon dioxide spacers 16 also causes a reduction in the dielectric properties thereof. Furthermore, the protruding bird's beak structures 18 of silicon dioxide spacers 16 hinder miniaturization efforts, due to the low dielectric properties and their pointed geometry which prohibits them from being densely packed. Miniaturization would necessitate that silicon dioxide spacers 16 be moved closer together. This would cause them to encroach on one another and would thereby alter the relationship of silicon dioxide spacers 16 with electronic devices enclosed by silicon dioxide spacers 16, such as transistors. This change in relationship caused by the encroachment of bird's beak structures 18 would result in gate oxides under the transistors being increased on one side unevenly so as to lower the speed and performance of the transistors.
It should be apparent from the above discussion that a need exists in the art for a method for forming patterned oxide regions that has a reduced amount of steps from conventional CVD deposition and that avoids formation of the bird's beak structures that result from conventional thermal oxidation. Such a method would be especially beneficial if oxide spacers and gate oxides with high dielectric properties could be formed with the method in a manner that would maintain or increase throughput of the MOS integrated circuit manufacturing process.